Trusted Microelectronics Special Topic: Field Programmable Gate Array (FPGA) Assurance Workshop
3/1/2017 - 3/2/2017
The MITRE Corporation
7525 Colshire Drive
McLean,  VA  22102
Event Type : Working Group
Event Code : 787B
NDIA is pleased to offer our ninth workshop designed to explore the special topic of FPGA assurance. At the request of Congress , DoD formed a Joint Federated Assurance Center (JFAC) to address assurance concerns in software and hardware. The JFAC has identified FPGAs as a hardware priority topic because of their pervasiveness and programmability. The Deputy Assistant Secretary of Defense for Systems Engineering (DASD(SE)) has established an FPGA Assurance Working Group, under the JFAC and with the support of the Trusted and Assured Microelectronics Initiative , to advise and make recommendations on matters related to the trust and assurance of FPGA technology used in DoD systems. The overall objective of the working group is to produce a coherent and focused strategy for achieving FPGA assurance in collaboration with industry and academia. Additionally, the working group seeks to promote awareness of current FPGA efforts, streamline and synchronize similar activities, and notify the JFAC Steering Committee of investment gaps.
The JFAC FPGA Assurance Working Group conducted an initial meeting that brought together major government stakeholders and subject matter experts, showcased some significant work from the defense, intelligence, and space communities, and offered different perspectives on what the issues are and possible solutions that the broader DoD community might leverage. The broad categories addressed during the meeting centered on threats, access, performance requirements, and assurance. Issues discussed highlighted a need to focus and collaborate on validation and verification for bitstream and third-party Intellectual Property (IP), the need for a better understanding of the relationship between FPGA hardware, software, and firmware, and appropriate assurance methods. An identified primary objective was to improve the information sharing and collaboration not only within the government, but with industry and academia. The objective of this workshop is to start an ongoing collaboration with industry.
Workshop format: This workshop will take place over two days, March 1st and 2nd, 2017. The morning of Day One, March 1st, will be set aside for a government only meeting led by the DoD FPGA Assurance team. The morning session is open only to government or Federally Funded Research and Development Center representatives. Day One afternoon will highlight briefings on progress to date on the DoD Assurance Efforts as well as series of panels. Day Two, March 2nd, will be organized around five breakout groups. These groups will be given a set of questions for consideration and discussion around the following topics:
Assuring the Supply of FPGAs
• Increasing confidence and assurance in FPGA supplies
• Maintaining Access
• Addressing unique/specialized needs (Rad Hard, long life cycles)
Assuring the firmware and IP for FPGAs
• Protecting against malicious tampering of firmware or IP theft of firmware
• Relationship to software assurance
• Validation/vetting of 3rd party IP
Assuring System Security when FPGAs are used
• Evolving FPGA security features and using them effectively
• System security architectures and approaches
Ensuring the Lifecycle when FPGAs are used
• Counterfeits/Clones and Piracy
• Protecting firmware over the lifecycle
• Protecting deployed systems with FPGAs
Leveraging other FPGA Communities
• Other industries with similar concerns (Automotive, Health, etc)
• Standards/ GIDEP
• Protecting proprietary interests
At the conclusion of the workshop there will be a report of the results from each breakout group and a proceedings of the meeting will be produced and distributed. These workshops are designed to be truly interactive and require full participant engagement.
Who should attend: Government, Industry and Academic providers, researchers and users of FGPAs and the FPGA ecosystem (including IP, etc.)
When registering, please be sure to also complete the survey found at the following link to express your interest in the breakout groups. Attendees will be assigned to breakout groups based on expressed interest and to balance the size of the groups. Trusted FPGA Breakout Session Survey
For more info contact firstname.lastname@example.org.